1. Field of the Invention
This invention relates to a method of fabricating a semiconductor device and in more particular to a method of fabricating a very fine and submicron trench isolation region.
2. Description of the Related Art
A method of fabricating conventional trench isolation regions will be described with reference to FIGS. 1A to 1F.
First, as shown in FIG. 1A, a field oxide film 2 is formed by selectively oxidizing the top surface of a P-type silicon substrate 1. Then a gate oxide film 3 is formed on the surface of the silicon substrate 1 at a prescribed position which will act at least as a memory cell in a semiconductor device. Consecutively, the whole surface of the semiconductor substrate including the field and gate oxide films 2 and 3 is covered with a polycrystalline silicon film 4 and a first oxide film 5 in order. Thereafter, as shown in FIG. 1B, a first resist film 6 is formed on the first oxide film 5, holes are made in prescribed positions of the resist film 6 corresponding to places which will act finally as trench isolation regions 7-1 to 7-3, and the first oxide film 5, the polycrystalline silicon film 4 and further the gate oxide film 3 are successively etched by using the first resist film 6 as a mask to cause the P-type silicon substrate 1 to be exposed. After the first resist film 6 is removed, as shown in FIG. 1C, the exposed silicon substrate is subjected to etching by using the first oxide film 5 as a mask to form trenches 8. Then, as shown in FIG. 1D, a second oxide film 9 and a third oxide film 10 are formed in order on the first oxide film 5 and the inner surfaces of the trenches 8 so that the oxide films 9 and 10 are completely buried in the trenches 8. In FIG. 1D, d.sub.1, d.sub.2 and d.sub.3 are defined to represent the final thickness of the third oxide film 10 at prescribed positions shown in the drawing, i.e. at any position above the gate oxide film 3, any position above a boundary between the gate oxide film 3 and the field oxide film 2 and any position above the field oxide film 2, respectively. Then, as shown in FIG. 1E, the third oxide film 10, the second oxide film 9 and the first oxide film 5 are subjected to etch back by using the polycrystalline silicon film 4 as a stopper so that the second oxide film 9 and the third oxide film 10 are selectively buried only in the trench isolation regions 7-1 to 7-3. Finally, as shown in FIG. 1F, a silicide film is deposited on the whole surface above the semiconductor substrate, which is followed by selectively removing the silicide film to thus form a silicide wiring 11. Consequently, transistors 12 having polycide gate electrodes formed in self-alignment with the trench isolation regions 7-1 to 7-3 are formed. The polycide gate electrode is of a stacking structure comprising the polycrystalline silicon film and the silicide film.
Generally, as for the third oxide film 10, there is used a BPSG film formed by a low pressure CVD method and having good coverage and high reflow property. However, after heat-treating, the thickness of the third oxide film 10 has the following relation: d.sub.2 &gt;d.sub.3 .apprxeq.d.sub.1 as shown in FIG. 1D. Thus the first oxide film easily remains at the position of d.sub.2 when the etch back is performed according to the conventional method, and over-etching must be performed to remove the remaining oxide film. When the over-etching is performed, the second and third oxide films buried in the trench are depressed and there is a possibility of a short circuit taking place between the silicide wiring and the silicon substrate. In addition, if an atmospheric pressure CVD method is used, the thickness of the third oxide film 10 has the following relation: d.sub.2 &gt;d.sub.3 &gt;&gt;d.sub.1, and thus the possible short circuit is more remarkable. A problem exists in that it is difficult to appropriately control the etch back step of burying the oxide films in the trenches according to the conventional method.